Microelectronic circuits have shrunk well into the sub-micron range, and their size continues to shrink even further with each passing generation of technology. This continued miniaturization can exacerbate problems that have occurred in previous technologies. One such problematic area is the silicon/gate oxide (Si/SiO2) interface. In spite of constant efforts to improve the quality of the gate oxide, it still can serve as a source of defects that can detrimentally affect the operation of a transistor. For example, because of the way in which the gate oxide is grown from single crystal silicon, different bonds and bonds lengths are present in the two different materials. This causes a lattice mismatch between the gate oxide material and the underlying silicon material, which is highest at the Si/SiO2 interface. Due to their proximity to the channel region, defects at the Si/SiO2 interface have the ability to scatter particles, and they can get electrically charged and create a potential at the interface. Electrons traveling through the channel can be diverted by this potential, which leads to a reduction in current, and in turn, lead to overall degradation of device performance.
Negative bias temperature instability is a degradation mechanism where the application of negative bias on the gate of a p-channel metal oxide semiconductor (PMOS) transistor leads to the creation of interface traps at the Si/SiO2 interface. Interface traps are electrically active defects with an energy distribution throughout the silicon band gap. They act as generation/recombination centers and contribute to leakage current, low-frequency noise, and reduced mobility, drain current, and transconductance. Additionally, the interface trap density induced by NBTI increases with decreasing oxide thickness. This oxide thickness dependence of interface trap generation implies that NBTI becomes more severe for ultra thin oxides, which are currently present in today's technologies. Further, NBTI stress-induced variances in digital device saturation drive current, due to channel degradation, can lead to significant timing issues. For example, if digital signals arrive at different times, signal processing becomes corrupted and ultimately results in circuit failure. NBTI can also be affected by the quality of the gate oxide. Thus, the number of traps or weak spots in the oxide must be minimized to reduce NBTI sensitivity and defects in general.
Accordingly, what is needed in the art is a process for addressing oxide defects attributable to Si/SiO2 lattice mismatch and NBTI.